Integrated circuits often make use of multiple interconnecting layers. Such arrangements reduce chip area for a given number of devices or circuit elements. In order to provide electrical contact between two layers, for example, contact vias may be etched through an interlayer dielectric during fabrication. Alternatively, straps may be formed connecting one layer to another layer. One form of these straps makes use of a "butting contact" 10 such as that illustrated in FIG. 1. Straps are also used for interconnection of other elements or layers, wherever oxide or other non-conducting gaps need to be bridged.
The vias or straps must be fabricated of conductive material in order to provide electrical communication between the layers. Although other conducting materials may be used, it is advantageous to employ a silicide such as titanium silicide (TiSi.sub.2) due to the low resistance or ohmic contact it forms with silicon, including both single crystal silicon and polycrystalline silicon. The latter material is often referred to as polysilicon, or poly.
Silicides have also been used for local interconnection, to provide low resistance electrical contact between device active regions within a silicon substrate (e.g., the drain of a MOSFET transistor) and other devices or conducting layers. Aluminum and other metals have lower sheet resistance than silicide. However, integration of these metals as a strap or local interconnect is difficult because of their high temperature instability and poor step coverage into contacts during deposition. The surface upon which the metal is to be deposited must be relatively smooth and therefore requires some type of planarization prior to metal deposition, which complicates the process. Additionally, many of the typical low-resistance metals also can contaminate the substrate in which the active devices are formed, causing parasitic leakage currents or device failure. For this reason, a diffusion barrier must also be formed to prevent diffusion of the metal ions to the silicon substrate. This also adds a level of complexity not required for alternative local interconnect materials. Thus, especially for narrow contacts formed in VLSI and ULSI circuits, silicide is increasingly used as a low resistance contact between device active areas and aluminum lines, or simply as the sole layer in a local interconnect.
For many interconnect applications, it is possible to employ a self-aligned silicidation process ("salicidation"). Salicidation is produced by depositing an elemental refractory metal layer, such as titanium, over silicon in any form, such as silicon substrates, amorphous silicon or polysilicon layers. Reaction between the titanium and the silicon takes place during a high temperature anneal or sinter step. The process is referred to as "self-aligned" because silicide forms only where the metal layer contacts silicon, for example, through contact openings. Ordinarily, salicidation is advantageous because silicide is formed exactly where it is desired, that is, over the polysilicon and substrate regions defined by a prior contact mask.
Salicidation, however, is sometimes difficult to perform. FIG. 1, for example, illustrates a butting contact opening 10 in an insulating layer 12, which covers a substrate 14, a first polysilicon layer 16, and a second polysilicon layer 18. The butting contact is well known and can be formed by a conventional photolithographic process and subsequent etch. Salicidation cannot ordinarily be employed to form a silicide strap across the polysilicon layers 16 and 18. It is often difficult to bridge an interlayer oxide layer 20 and a sidewall spacer 22. The spacer 22 forms as a byproduct of the contact etch.
FIG. 2 shows a strap 30 which would result if conventional salicidation techniques were applied to the butting contact 10 across two relatively thick polysilicon layers 16 and 18. After etching the contact opening 10 (FIG. 1) and depositing a layer of elemental titanium, a first sinter step results in the silicide strap 30 forming across the contact opening 10 (FIG. 2). A layer of unreacted titanium metal 32 and a layer of titanium nitride (TiN) byproduct 34 would next be selectively removed by processes known to this art. A final sinter may be performed to lower the silicide's sheet resistance to acceptable levels by converting the titanium from the C49 phase to the lower resistance C54 phase.
In the first place, either the thickness of deposited titanium needs to be carefully controlled, or the sinter time needs to be strictly controlled to avoid overconsumption of the underlying silicon. Overconsumption would result in poor contact between the polysilicon layers and the strap. Even if overconsumption is avoided, the resulting strap 30 would be fragile. Though illustrated as spanning the gap formed by the interlayer oxide 20 and the oxide spacer 22, the strap 30 becomes very thin at a bridge 36 over the oxide spacer 22. This narrow bridge 36 would naturally demonstrate very high resistivity or would in practice be subject to mechanical failure (breakage).
The bridge 36 is too thin due to a lack of silicon to feed the salicidation process. Since salicidation consumes the underlying silicon in order to form TiSi.sub.2, spanning thin polysilicon layers with this method would pose even more difficulty. An intrinsic resistor or a thin film transistor, for example, might be formed from a very thin silicon layer 54 (see FIG. 3). The thin polysilicon layer 54 cannot supply the correct proportion of silicon to titanium for salicidation over the thin layer 54. The strap produced by a standard salicidation process would be metal-rich and thus indistinguishable from other metal byproducts for purposes of the selective etch following the first sinter.
Because of these problems, manufacturers desiring straps across thin or thick polysilicon layers have necessarily resorted to alternatives other than salicidation. Traditionally, conductive straps have been fabricated through deposition techniques. Polysilicon or metal, for example, can be deposited into a contact opening directly onto the polysilicon layers and the substrate by co-sputtering, co-evaporation or chemical vapor deposition (CVD) techniques. Depositing silicide is costly, however, due to the requirement of an extra mask. A mask is necessary either for depositing the silicide at appropriate points on the circuit, or for etching away unwanted silicide. In either case, space is wasted in providing leeway for misalignment of the mask.
Salicide cladding over the substrate to form local interconnect can also be problematic. FIG. 2 illustrates simultaneous formation of a cladding 44 along with the salicided strap 30, discussed above. Salicidation over a thin active region 46, in order to provide ohmic contact to both the underlying active area 46 and to metal lines or to other circuit nodes (not shown), also consumes silicon of the substrate 14. During anneal, silicon from the substrate 14 dissolves into the overlying metal layer. Dissolution is not uniform, though, and as a result metallic spikes 48 are formed in the thin active region 46, interfering with the device's p-n junction. To remedy this situation, a polysilicon or amorphous silicon layer may be provided between the device active region and the refractory metal layer. However, an additional mask step is required to ensure correct alignment of the deposited silicon layer, increasing fabrication expense.
It is thus an object of the present invention to provide a self-aligned silicide strap for connection of thin polysilicon layers in an integrated circuit.
It is a further object of the present invention to provide such a strap without requiring post-salicidation masks for patterning the silicide.
It is a still further object of the present invention to reduce junction spiking during metallization of device active regions.